This application claims priority from Canadian Patent Application No. 2,342,496, filed Mar. 30, 2001.
The present invention relates to semiconductor memory arrays. More particularly the invention relates to wordline strap configurations for increasing wordline packing density and reducing the size of the semiconductor memory array.
High density memory integrated circuits, in particular dynamic random access memory (DRAM) circuits arid nonvolatile memory circuits such as flash or read only memory (ROM), contain large rectangular arrays of cells, each of which represents a single bit of memory storage. Digital information is written to and read from these cells by peripheral circuitry that addresses each cell through wordlines and bitlines. In a typical DRAM, each storage cell consists of a polysilicon gate metal oxide silicon field effect transistor (MOSFET) and a capacitor. A wordline comprises a continuous line of gate level polysilicon passing alternately over field oxide and over the channel regions of access MOSFETs in the string of memory cells addressed by the wordline. Switching a voltage signal on the wordline from a low to a high voltage turns the access MOSFETs on (for n-channel MOSFETs) and electrically connects the cell""s storage capacitor to a bitline for sensing (i.e. accessing the cell). Switching from the high down to the low voltage ends the access. Hence, taking the wordline from low to high or from high to low is the critical criterion for cell access times. The performance of the DRAM array is dependent upon the speed with which these voltage transitions take place. That speed in turn depends upon the RC (resistance-capacitance) time constant of the wordline.
In order to achieve high performance, the resistive component R must be as small as possible. As a conductor polysilicon, even heavily doped, cannot compare with metals such as, for example, aluminum. Various suicides have been used in DRAM gate polysilicon technology (e.g. WSix, TaSix, MoSix) to reduce tie sheet resistance and improve wordline speed. These silicides typically have 8-15xcexa9/xe2x96xa1 (ohms per square) sheet resistances. Unfortunately, the much, lower sheet resistance in in-situ formed silicides/salicides (TiSix and CoSix) are difficult to apply to DRAM wordlines because the high temperature steps involved in DRAM cell formation cause their conductance to degrade.
As requirements on DRAM speeds have become more demanding and arrays become larger, tile need for reducing the resistivity of wordlines has become even more important. A solution that has met with considerable success is the strapping of the polysilicon wordlines with lines formed in a superjacent metal level, for example aluminum or tungsten. The selected metallization level can be any wiring level above the polysilicon wordlines except the level used to form bitlines (if metal bitlines are used). Practically, in order to avoid unnecessary interconnections, the next available higher level has been preferred. Ideally, the metal straps should be identical to maintain the same performance and behaviour across the wordline addresses.
The sheet resistances of the metal lines are tens to hundreds of mxcexa9/xe2x96xa1 making them very effective in reducing the RC time constant of wordlines. The strapping is accomplished by forming a metal line in a metallization level lying directly over and running parallel with the polysilicon wordline and spaced from it by an insulative layer. Periodic contacts between the lines direct most of the current flow through the low resistance metal lines.
In conventional wordline strapping, metal lines are formed in a single metallization levels, for example a first aluminum level. The metal lines are stitched to underlying polysilicon word lines which lie directly below the metal lines, by meals of interlevel contacts or vias. The pitch of the metal lines is defined as the distance between one point on a line and a corresponding point on an adjacent line.
Advances in fabrication technology have permitted an increase in memory array density and a decrease in polysilicon wordline pitch. Unfortunately, the design rules for the metal lines do not permit a corresponding decrease in the pitch of the metal lines, particularly as 0.18 xcexcm technology has come to the fore. Techniques such as a boosted dual wordline design scheme have been used to relax the metal design rule and improve the circuit yield. However, such designs require additional sub-wordline drivers and drive lines. Therefore, memory array wordline density is limited by the metal pitch.
The narrow pitch required of metal level lines formed in a single metal level limits their practical width and thereby limits their resistivity. By stitching the polysilicon wordlines alternatively to two levels of metallization, the pitch can be doubled. Metal lines are formed in two metallization levels. The pitch on each metallization level is twice the pitch as compared to when only a single metallization level is used. Doubling the pitch allows, not only relaxation of the design rule, but also permits broadening large portions of the lines on each level, thereby lowering their resistance.
Many modern DRAMs avoid wordline strapping entirely in order to avoid tight metal pitches in the array. Instead they rely on splitting the wordlines into many individually driven sections called sub-wordlines. These sub-wordlines are short enough (e.g. 256 to 1024 cells) so that they do not require straps to achieve sufficient speed. However, the individual drivers occupy valuable chip area. It is therefore desirable to have as many cells as possible on a given sub-wordline.
Another difficulty that has arisen with the ever-increasing size and density of memory arrays is the increased coupling capacitance between signal lines, such as wordlines and bitlines. Coupling noise is very sensitive to scaling and is considered a significant obstacle to achieving reliable high-speed and high-density memory arrays. One technique used to balance the effects of the narrow packing of the signal lines is to xe2x80x9ctwistxe2x80x9d them by interconnecting to different metal lines over their length. Various twisting configurations exist such that each wordline follows an identical path over its length, and is exposed to the same inter-line coupling effects. No arrangement has previously been proposed that permits both multilevel wordline strapping, and wordline twisting.
Therefore, there is a need for a wordline layout that provides fast wordline access while increasing the wordline packing density and reducing capacitive coupling effects.
The object of the present invention is to mitigate or obviate at least one disadvantage of previous strap layouts. In particular, it is an object of the present invention to provide a densely packed twisted signal line arrangement in a semiconductor memory array, such as a DRAM memory array.
In a first aspect, there is provided a wordline strapping arrangement for a semiconductor memory array. A plurality of wordlines are formed in a polysilicon layer of the semiconductor memory array, and conductive stitches are formed in a first conductive layer overlaying the polysilicon layer. The stitches have a predetermined configuration in each of successive stitching regions, and are coupled to the plurality of wordlines in each of the successive stitching regions, to provide an effective twisting of the plurality of wordlines such that the physical characteristics of the wordlines are balanced over their length. At least one bypass strap is formed in a second conductive layer superjacent the polysilicon layer. The bypass strap is coupled to successive ones of the stitches in each successive stitching region. Primary straps are formed in a third conductive layer superjacent the polysilicon layer. The primary straps in this third conductive layer are coupled, in each of the successive stitching regions, to the stitches not coupled to the bypass strap.
According to a presently preferred embodiment, there are four successive stitching regions. The first conductive layer is adjacent the polysilicon layer, the third conductive layer overlays the first conductive layer, and the second conductive layer overlays the third conductive layer. Strap stitches are formed in a fourth conductive layer, interposed between the second and third conductive layers, to provide interconnections between the primary straps and the at least one bypass strap in each successive stitching region. In this manner, each wordline can be coupled, in turn, to the bypass strap. In combination with the interconnection of the stitches to the primary straps, this coupling of each wordline to the bypass strap and the primary straps form a balanced twisted logical signal line for each wordline. Preferably, the primary straps occupy substantially the same pitch as the wordlines. For example, where there are three primary straps, and one bypass strap, the three primary straps can occupy the same pitch as four wordlines.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of die following description of specific embodiments of the invention in conjunction with the accompanying figures.